There has been known so far a panel that produces a display by controlling a gaseous discharge for each display cell, such as a plasma display panel. For normal discharge in such a display panel it is necessary that charges stored be always held in a state suitable for discharge. To this end, it is customary in the art to regularly initialize all the display cells as by removing stored charges that trigger an unintended discharge.
Such initialization schemes are described, for example, in JP-A-10-143106, JP-A-8-278766, JP-A-7-140927, JP-A-9-325736 and JP-A-8-212930.
While various initialization schemes have thus been proposed, it is required to perform initialization that matches each particular discharge stricture, discharge condition and panel driving method.
The inventor of the present invention has filed a patent application on an initialization sequence including a negative reset pulse (Japanese Pat. Appln. Hei 10-276735 filed Sep. 30, 1998; U.S. application Ser. No. 09/261,260 filed Mar. 3, 1999). This case is an improvement on his previous invention.
A description will be given first of the invention described in the above patent application.
FIG. 16 is a diagram schematically depicting a gaseous discharge display panel and its drive circuit in their entirety.
The panel has 640 by 480 pixels arranged in a matrix form. Unit panels 11, 12, . . . 140, 21, 22, . . . 240, . . . , 301, 302, . . . 3040, each consisting of 16 by 16 pixels, are arranged with 40 rows and 30 columns to form the panel in its entirety.
Each electrode is connected to a common electrode and a discrete electrode. By controlling the voltage of the discrete electrode while applying display pulses to the common electrode, discharge at each pixel is controlled to thereby perform ON/OFF control of display.
And 640 by 480 pieces of data necessary for controlling the voltages of the discrete electrodes of the entire panel are input as data of one frame to a video interface circuit 100.
The data of one frame is provided from the video interface circuit 100 to the unit panels via 30 bus circuits 101, 102, . . . , 130.
The first bus circuit 101 extracts 640 by 16 pieces of data from the 640 by 480 pieces of data, and sends them to the 40 unit panels 11, 12, . . . , 140. Based on addresses assigned to the data, the unit panels 11, 12, . . . , 40 each receive 16 by 16 pieces of data.
In the unit panels 11, 12, . . . , 140 one piece of data is allocated to each pixel by a drive shift register to control the voltage of the discrete electrode. Each piece of data consists of 24 bits. They are eight bits for R (red), eight bits for G (green) and eight bits for B (blue). The 8-bit data is used to control the brightness of display in 256 steps.
The other bus circuits 102, . . . , 130 also respectively extract 640 by 16 pieces of data and send them to the unit panels 21, 22, . . . , 240, . . . , 301, 302, . . . ,3040. And the unit panels 21, 22, 240, 301, 302, . . . , 3040 each receive 16 by 16 pieces of data and control voltages of discrete electrodes of the 16 by 16 pixels.
The 640 by 480 pieces of data of one frame are input as data of one frame during pulse intervals of a vertical sync signal V. sync shown in FIG. 17(a). A horizontal sync signal H. sync shown in FIG. 17(b) is generated 480 times per frame. A single horizontal sync signal H. sync is followed by 640 pieces of data being input.
In this display panel each display cell is connected to the common electrode and the discrete electrode; the discrete electrode is driven for each display cell and the common electrode is driven in common to plural cells. And display pulses are applied to the common electrode and the application of a positive control voltage by the discrete electrode is controlled for each cell, by which a discharge is controlled for each display cell to provide a display. The display pulse of the common electrode and the control voltage of the discrete electrode are produced for each unit panel and provided to each display cell.
FIG. 18 depicts the common electrode-applied display pulse, the discrete electrode control voltage and discharge waveform for each frame. FIG. 18 shows the case of a stable discharge. Each frame starts with an initialization sequence, followed by display sequences.
In the duration of one display pulse the discharge is generated twice. The first discharge is a storage discharge and the second an erasing discharge. Positive rise-up of the discrete electrode control voltage stops the discharge. The rise-up timing of the discrete electrode control voltage is controlled by the 8-bit data in 256 steps. Accordingly, the brightness of display is also controlled in 256 steps. When the positive rise-up timing of the discrete electrode control voltage is brought forward, the frequency of occurrence of the discharge decreases, reducing the brightness of display.
FIG. 19 is a diagram showing the relationship between the voltage of the common electrode and the discharge in the initialization sequence depicted in FIG. 18. The left-hand side is the common electrode and the right-hand side the discrete electrode.
The display pulse is formed by a two-step voltage, which increases and decreases in stages; the absolute value of the voltage of a reset pulse may preferably be set above the first-stage voltage value of the display pulse. With such a display pulse, it is possible to cause two discharges, i.e. a charge storage discharge and a stored charge removal discharge, by one shot of the display pulse. Then, when a stable discharge takes place, no reset pulse needs to be inserted.
Incidentally, it is preferable to apply the reset pulse once for each or plural frames. This provides frames free from the necessity of inserting reset pulses, imparting flexibility to the processing involved.
Potentials and charges of the both electrodes at times (1) through (6) are described below. The left-hand side is the common electrode and the right-hand side the discrete electrode.
At time (1) the voltages of the both electrodes are 0 V, and no discharge occurs. At time (2) the voltage of the common electrode reaches 360 V, causing a discharge. This is the storage discharge. Negative charges resulting from the discharge are attracted to the common electrode, whereas positive charges are attracted to the discrete electrode. At time (3), the effective voltage of the common electrode drops below 360 V due to the negative charges attracted thereto, stopping the discharge. At time (4), when the voltage of the common electrode is reduced down to 0 V, a discharge is caused by the potential difference between the both electrodes due to the charges attracted to them. This is removal discharge. At time (5) the discharge stops and the stored charges also disappear. At time (6) a reset pulse of −180 V is applied to the common electrode, but no change occurs since no stored charges exist in this case.
The common electrode in this display panel is driven using a complex display pulse whose voltage changes in two stages. And the charge storage discharge and the stored charge removal discharge are carried out by a single shot of this complex display pulse. Accordingly, it is possible, theoretically, that charges are automatically removed even if the display discharge is repeated. In practice, however, charges are stored and remain unremoved due to insufficient voltage application and the repetition of charge and discharge operations, resulting in the display becoming unstable.
As a solution to this problem, it is conventional to initialize the discharge cell condition through the inversion of charges at the display cell by applying a positive pulse to every discrete electrode once per frame or frames, or applying a negative pulse (a reset pulse) during intervals between successive applications of display pulses to the common electrode. The application of one complex display pulse and one reset pulse is referred to as an initialization sequence.
FIGS. 20 and 21 are diagrams showing how charges stored by an unstable discharge are removed by the reset pulse.
FIG. 20 shows the display pulse to the common electrode and the discrete electrode control voltage and the discharge waveforms in one frame. What are depicted in FIG. 20 are the same as those in FIG. 18 except that a discharge is caused by the reset pulse of the initialization sequence.
FIG. 21 shows the relationship between the voltage and discharge at the common electrode in the initialization sequence depicted in FIG. 20. The operations at times (1) through (4) are the same as in FIG. 19. At time (5) negative charges are stored on the common electrode due to an unstable discharge. Even if the display pulse of 360 V is applied to the common electrode in the next cycle (2) while leaving the negative charges unremoved, the effective voltage of the common electrode does not reach 360 V, and a discharge is hard to occur. Then, at time (6) the reset pulse of −160 V is applied to the common electrode to discharge the stored charges. At time (7) after the discharge positive charges are attracted to the common electrode, and negative charges are attracted to the discrete electrode. Since the positive charges are stored on the common electrode, its discharge will not be hindered by the stored charges when the display pulse is applied to the common electrode in the next display cycle (2). In this instance, since the stored charges on the common electrode are positive, the application of the display pulse raises its effective voltage above the applied voltage, facilitating the discharge. This gives rise to another problem. The display pulse is applied at 160 to 180 V in the first stage and 320 to 360 V in the second stage; however, facilitating the discharge by the stored charges leads to the occurrence of a false discharge in the first stage.
In controlling the entire display panel, characteristic variations are caused in the panel according to its manufacturing conditions, and only with the above-mentioned discharge stabilization scheme, it is impossible to provide a sufficient voltage width (margin) for control, giving rise to the problem of false discharge. Further, characteristic variations are also present for each panel; to solve these problems, it is necessary to maintain stable discharge and provide a sufficient margin.
Moreover, the initialization sequence is effective for a cell in an unstable state, but it means a voltage change ineffective for stable discharge, sometimes making the stable discharge unstable. Accordingly, it is necessary that the initialization sequence be adapted not to affect the stable cell.
Additionally, data to be provided to the discrete electrode for individual control of each cell is usually transferred from a logic circuit, and a high voltage driver IC is used to control the cell. At this time, high-voltage switching on the part of the common electrode causes noise in no small way, which affects the data by the logic circuit, leading to a false display. Accordingly, it is necessary to reduce noise in the sequence for the common electrode and the transfer of data for each cell.